[Home ]   [ فارسی ]  
Main Menu
Home::
About::
Research::
People::
Facilities::
Sientific Nwes & Events::
Contact Us::
Useful links::
Photo Album::
Research Lab.::
::
Search in website

Advanced Search
..
Polling
How do you evaluate this site?
Good
Avrage
poor
   
..
IJEEE

AWT IMAGE

..
:: An Approximate Carry Disregard Multiplier with Improved Mean Relative Error Distance and Probability of Correctness ::
 | Post date: 2023/12/14 | 
 

An Approximate Carry Disregard Multiplier with Improved Mean Relative Error Distance and Probability of Correctness

N. Amirafshar
School of Electrical Engineering
Iran University of Science and Technology
Tehran, Iran
A.S. Baroughi
School of Electrical Engineering
Iran University of Science and Technology
Tehran, Iran
H. S. Shahhoseini
School of Electrical Engineering
Iran University of Science and Technology
Tehran, Iran
N. TaheriNejad
TU Wien
Vienna, Austria

PDF     │   Abstract   │  Keywords   │  References   │  Cite This

Abstract:
Nowadays, a wide range of applications can tolerate certain computational errors. Hence, approximate computing has become one of the most attractive topics in computer architecture. Reducing accuracy in computations in a premeditated and appropriate manner reduces architectural complexities, and as a result, performance, power consumption, and area can improve significantly. This paper proposes a novel approximate multiplier design. The proposed design has been implemented using 45 nm CMOS technology and has been extensively evaluated. Compared to existing approximate architectures, the proposed approximate multiplier has higher accuracy. It also achieves better results in critical path delay, power consumption, and area up to 47.54 %, 75.24%, and 92.49%, respectively. Compared to the precise multipliers, our evaluations show that the critical path delay, power consumption, and area have been improved by 39%, 18%, and 6 %, respectively.

Keywords: Approximate computing; Multiplier; High performance; Power Efficient; Area Efficient

References:
[1] C. Ossimitz and N. TaheriNejad, "A Fast Line Segment Detector Using Approximate Computing," 2021 IEEE International Symposium on Circuits and Systems (ISCAS), Daegu, Korea, 2021, pp. 1-5, doi: 10.1109/ISCAS51556.2021.9401660.
[2] S. E. Fatemieh, M. R. Reshadinezhad and N. TaheriNejad, "Approx- imate in-memory computing using memristive imply logic and its application to image processing", 2022 IEEE International Symposium on Circuits and Systems (ISCAS), pp. 1-5, 2022.
[3] U. Lorrič, R. Pilipović and P. Bulic, "A hybrid radix-4 and approximate logarithmic multiplier for energy efficient image processing", Electron-ics, vol. 10, no. 10, 2021.
[4] B. Garg and Y. Bisht, "A Novel High Performance Reverse Carry Propagate Adder for Energy Efficient Multimedia Applications," 2019 IEEE International Symposium on Smart Electronic Systems (iSES) (Formerly iNiS), Rourkela, India, 2019, pp. 296-299, doi: 10.1109/iSES47678.2019.00073.
[5] F. Tu, S. Yin, P. Ouyang, L. Liu and S. Wei, "Reconfigurable Architecture for Neural Approximation in Multimedia Computing," in IEEE Transactions on Circuits and Systems for Video Technology, vol. 29, no. 3, pp. 892-906, March 2019, doi: 10.1109/TCSVT.2018.2812781.
[6] P. Yin, C. Wang, H. Waris, W. Liu, Y. Han and F. Lombardi, "Design and Analysis of Energy-Efficient Dynamic Range Approximate Logarithmic Multipliers for Machine Learning," in IEEE Transactions on Sustainable Computing, vol. 6, no. 4, pp. 612-625, 1 Oct.-Dec. 2021, doi: 10.1109/TSUSC.2020.3004980.
[7] X. Hu, T. Chen, H. Huang, Z. Liu, X. Li and X. Xiong, "Efficient field-programmable gate array-based reconfigurable accelerator for deep convolution neural network", Electronics Letters, vol. 57, no. 6, pp. 238-240, 2021.
[8] A. Pothen, S. M. Ferdous and F. Manne, "Approximation algorithms in combinatorial scientific computing", Acta Numerica, vol. 28, pp. 541-633, 2019.
[9] B. Grigorian and G. Reinman, "Accelerating divergent applications on SIMD architectures using neural networks", ACM Transactions on Architecture and Code Optimization (TACO), vol. 12, no. 1, pp. 1-23, 2015.
[10] A. Garofalo, G. Tagliavini, F. Conti, L. Benini and D. Rossi, "XpulpNN: Enabling Energy Efficient and Flexible Inference of Quantized Neural Networks on RISC-V Based IoT End Nodes," in IEEE Transactions on Emerging Topics in Computing, vol. 9, no. 3, pp. 1489-1505, 1 July-Sept. 2021, doi: 10.1109/TETC.2021.3072337.
[11] I. Hubara, M. Courbariaux, D. Soudry, R. EI- Yaniv and Y. Bengio, "Quantized neural networks: Training neural networks with low precision weights and activations", Journal of Machine Learning Research, vol. 18, no. 187, pp. 1-30, 2018.
[12] B. Jacob et al., "Quantization and Training of Neural Networks for Efficient Integer-Arithmetic-Only Inference," 2018 IEEE/CVF Conference on Computer Vision and Pattern Recognition, Salt Lake City, UT, USA, 2018, pp. 2704-2713, doi: 10.1109/CVPR.2018.00286.K. Wang, Z. Liu, Y. Lin, J. Lin and S. Han, "HAQ: Hardware-Aware Automated Quantization With Mixed Precision," 2019 IEEE/CVF Conference on Computer Vision and Pattern Recognition (CVPR), Long Beach, CA, USA, 2019, pp. 8604-8612, doi: 10.1109/CVPR.2019.00881.
[13] K. Wang, Z. Liu, Y. Lin, J. Lin and S. Han, "HAQ: Hardware-aware automated quantization with mixed precision", 2019 IEEE/CVF Conference on Computer Vision and Pattern Recognition (CVPR), pp. 8604-8612, 2019.
[14] J. Lee, H. Seo, H. Seok and Y. Kim, "A Novel Approximate Adder Design Using Error Reduced Carry Prediction and Constant Truncation," in IEEE Access, vol. 9, pp. 119939-119953, 2021, doi: 10.1109/ACCESS.2021.3108443.R. Nayar, P. Balasubramanian and D. L. Maskell, "Hardware Optimized Approximate Adder with Normal Error Distribution," 2020 IEEE Computer Society Annual Symposium on VLSI (ISVLSI), Limassol, Cyprus, 2020, pp. 84-89, doi: 10.1109/ISVLSI49217.2020.00025.
[15] P. Balasubramanian, R. Nayar and D. Maskell, "Approximate Array Multipliers", Electronics, vol. 10, pp. 630, 2021
[16] W. Choi, M. Shim, H. Seok and Y. Kim, "DCPA: Approximate adder design exploiting dual carry prediction", IEICE Electronics Express, vol. 18, no. 23, pp. 20210431-20210431, 2021.
[17] G. Anusha and P. Deepa, "Design of approximate adders and multipliers for error tolerant image processing", Microprocessors and Microsystems, vol. 72, pp. 102940, 2020.
[18] H. Seok, H. Seo, J. Lee and Y. Kim, "COREA: Delay- and energy-efficient approximate adder using effective carry speculation", Electron-ics, vol. 10, no. 18, 2021.
[19] S. Ullah, S. Rehman, B. S. Prabakaran, F. Kriebel, M. A. Hanif, M. Shafique, et al., "Area-optimized low-latency approximate multipliers for FPGA-based hardware accelerators" in Proceedings of the 55th Annual Design Automation Conference ser. DAC '18, New York, NY, USA:Association for Computing Machinery, 2018.
[20]R. Nayar, P. Balasubramanian and D. L. Maskell, "Hardware optimized approximate adder with normal error distribution" in 2020 IEEE Computer Society Annual Symposium on VLSI (ISVLSI), Los Alamitos, CA, USA:IEEE Computer Society, pp. 84-89, jul 2020.
[21] S. Vahdat, M. Kamal, A. Afzali-Kusha and M. Pedram, "TOSAM: An Energy-Efficient Truncation- and Rounding-Based Scalable Approximate Multiplier," in IEEE Transactions on Very Large Scale Integration (VLSI) Systems, vol. 27, no. 5, pp. 1161-1173, May 2019, doi: 10.1109/TVLSI.2018.2890712.H. Jiang, F. J. H. Santiago, H. Mo, L. Liu and J. Han, "Approximate Arithmetic Circuits: A Survey, Characterization, and Recent Applications," in Proceedings of the IEEE, vol. 108, no. 12, pp. 2108-2135, Dec. 2020, doi: 10.1109/JPROC.2020.3006451.
[22] H. Waris, C. Wang, W. Liu and F. Lombardi, "AxSA: On the design of high-performance and power-efficient approximate systolic arrays for matrix multiplication", Journal of Signal Processing Systems, vol. 93, no. 6, pp. 605-615, 2021.
[23] H. Jiang, F. Santiago, H. Mo, L. Liu and J. Han, "Approximate arithmetic circuits: A survey characterization and recent applications", Proceedings of the IEEE, pp. 1-28, 2020.
[24] O. Akbari, M. Kamal, A. Afzali-Kusha and M. Pedram, "Dual-Quality 4:2 Compressors for Utilizing in Dynamic Accuracy Configurable Multipliers," in IEEE Transactions on Very Large Scale Integration (VLSI) Systems, vol. 25, no. 4, pp. 1352-1361, April 2017, doi: 10.1109/TVLSI.2016.2643003.P. J. Edavoor, S. Raveendran and A. D. Rahulkar, "Approximate Multiplier Design Using Novel Dual-Stage 4:2 Compressors," in IEEE Access, vol. 8, pp. 48337-48351, 2020, doi: 10.1109/ACCESS.2020.2978773.M. Ha and S. Lee, "Multipliers With Approximate 4–2 Compressors and Error Recovery Modules," in IEEE Embedded Systems Letters, vol. 10, no. 1, pp. 6-9, March 2018, doi: 10.1109/LES.2017.2746084.
[25] P. J. Edavoor, S. Raveendran and A. D. Rahulkar, "Approximate multiplier design using novel dual-stage 4:2 compressors", IEEE Access, vol. 8, pp. 48337-48351, 2020.
[26] M. Ha and S. Lee, "Multipliers with approximate 4–2 compressors and error recovery modules", IEEE Embedded Systems Letters, vol. 10, no. 1, pp. 6-9, 2018.
[27] A. Gorantla and D. P, "Design of approximate compressors for multi-plication", J. Emerg. Technol. Comput. Syst., vol. 13, no. 3, april 2017.
[28] A. Momeni, J. Han, P. Montuschi and F. Lombardi, "Design and Analysis of Approximate Compressors for Multiplication," in IEEE Transactions on Computers, vol. 64, no. 4, pp. 984-994, April 2015, doi: 10.1109/TC.2014.2308214.S. Hashemi, R. I. Bahar and S. Reda, "DRUM: A Dynamic Range Unbiased Multiplier for approximate applications," 2015 IEEE/ACM International Conference on Computer-Aided Design (ICCAD), Austin, TX, USA, 2015, pp. 418-425, doi: 10.1109/ICCAD.2015.7372600.
[29] S. Hashemi, R. I. Bahar and S. Reda, "DRUM: A dynamic range unbiased multiplier for approximate applications", 2015 IEEE/ACM International Conference on Computer-Aided Design (ICC AD), pp. 418-425, 2015.
[30] S. Narayanamoorthy, H. A. Moghaddam, Z. Liu, T. Park and N. S. Kim, "Energy-Efficient Approximate Multiplication for Digital Signal Processing and Classification Applications," in IEEE Transactions on Very Large Scale Integration (VLSI) Systems, vol. 23, no. 6, pp. 1180-1184, June 2015, doi: 10.1109/TVLSI.2014.2333366.
Cite this paper as:
N. Amirafshar, A. S. Baroughi, H. S. Shahhoseini and N. TaheriNejad, "An Approximate Carry Disregard Multiplier with Improved Mean Relative Error Distance and Probability of Correctness," 2022 25th Euromicro Conference on Digital System Design (DSD), Maspalomas, Spain, 2022, pp. 46-52, doi: 10.1109/DSD57027.2022.00016.
 
View: 322 Time(s)   |   Print: 68 Time(s)   |   Email: 0 Time(s)   |   0 Comment(s)
کلیه حقوق مادی و معنوی این سایت متعلق به پژوهشکده الکترونیک می باشد . نقل هرگونه مطلب با ذکر منبع بلامانع می باشد .